Static timing analysis (STA) is performed in the development stage of a semiconductor integrated circuit. In STA, circuit timing is analyzed and verified based on a delay assigned to each element of a digital circuit. To improve the accuracy of such delay analysis, statistical timing analysis has been employed in recent years.
In the related art, during the development of a semiconductor integrated circuit, timing analysis is performed to verify or ensure the operation of a logical circuit. During the timing analysis, a delay value for each element of the logical circuit is calculated, and a delay accumulation value for a signal transmission path is calculated based on the delay value of each element. Then, static timing analysis (STA) is performed to analyze the pulse width of a signal at an input terminal of a flip-flip circuit or a memory. The logical circuit is corrected by referring to a timing report generated based on the STA results.
Factors affecting the delay time of elements include processes for forming transistors and wires of the semiconductor integrated circuit in addition to power supply voltages and temperatures. The calculation of the delay values takes into consideration a coefficient showing on-chip variation (OCV) of each of these factors. The STA is performed using the calculated delay values to verify whether the semiconductor integrated circuit functions normally when the circuit has on-chip variation.
In the timing analysis described above, delay variations occurring in instances (cells) forming a certain path is accumulated in the order in which a signal is propagated through the path. The accumulated value is used in the timing analysis. In this case, the timing verification is performed under an extremely strict condition that would be unrealistic for an actual circuit. Thus, much time is required for timing closure. As a result, design development takes a long time.
In recent years, variations for each of these factors are handled as a statistical probability during a timing analysis (refer, for example, to Japanese Laid-Open Patent Publication No. 2005-019524). With this method, the timing verification is performed under a more moderate condition. This reduces pessimism or achieves timing closure in a relatively simple manner.
Although the analysis method described in the above publication uses cell characteristic distributions within the circuit that are extracted through, for example, Monte Carlo analysis, the analysis method does not take into consideration changes in delays that occur in accordance with the location of each element on the chip. Thus, the results of the delay analysis are not correlated with circuit timing on an actual chip. Further, the analysis method described in the above publication does not take into consideration delays resulting from characteristics unique to each cell, the input and output slew rate, and delays of the entire path formed by a plurality of cells. Accordingly, the timing analysis tends to have a low accuracy.